Design Elements

exception seqlogic.DesignError

Design Error.

exception seqlogic.AssumeError

exception seqlogic.AssertError

class seqlogic.Module(name: str, parent: Module | None = None)

Hierarchical, branch-level design component.

A module contains: * Submodules * Ports * Local variables * Local processes

build() → None

main() → TaskCoro

Add design processes to the simulator.

property scope: str

Return the branch’s full name using dot separator syntax.

dump_waves(waves: defaultdict[int, dict], pattern: str)

Dump design elements w/ names matching pattern to waves dict.

dump_vcd(vcdw: VCDWriter, pattern: str)

Dump design elements w/ names matching pattern to VCD file.

input(name: str, dtype: T) → Packed

output(name: str, dtype: T) → Packed

connect(**ports)

logic(name: str, dtype: T, shape: tuple[int, ...] | None = None) → Packed | Unpacked

submod(name: str, mod: T) → T

drv(cf: Callable[[...], TaskCoro], *args: Any, **kwargs: Any)

mon(cf: Callable[[...], TaskCoro], *args: Any, **kwargs: Any)

combi(ys: Value | Sequence[Value], f: Callable[[...], Array | str | tuple[Array | str, ...]], *xs: Packed | Unpacked)

Combinational logic.

expr(y: Value, ex: Expr)

Expression logic.

assign(y: Value, x: Packed | str)

Assign input to output.

dff(q: Packed, d: Packed, clk: Packed[Scalar], en: Packed[Scalar] | None = None, rst: Packed[Scalar] | None = None, rval: T | str | None = None, rsync: bool = False, rneg: bool = False)

D Flip Flop with enable, and reset.

Parameters:

• q – output

• d – input

• clk – clock w/ positive edge trigger

• en – enable

• rst – reset

• rval – reset value

• rsync – reset is edge triggered

• rneg – reset is active negative

mem_wr(mem: Unpacked, addr: Packed, data: Packed, clk: Packed[Scalar], en: Packed[Scalar], be: Packed | None = None)

Memory with write enable.

assume_func(name: str, p: Expr, f, xs, clk: Packed[Scalar], rst: Packed[Scalar], rsync: bool = False, rneg: bool = False, msg: str | None = None) → Assumption

assert_func(name: str, p: Expr, f, xs, clk: Packed[Scalar], rst: Packed[Scalar], rsync: bool = False, rneg: bool = False, msg: str | None = None) → Assertion

assume_expr(name: str, p: Expr, q: Expr, clk: Packed[Scalar], rst: Packed[Scalar], rsync: bool = False, rneg: bool = False, msg: str | None = None) → Assumption

assert_expr(name: str, p: Expr, q: Expr, clk: Packed[Scalar], rst: Packed[Scalar], rsync: bool = False, rneg: bool = False, msg: str | None = None) → Assertion

assume_seq(name: str, p: Expr, s, xs, clk: Packed[Scalar], rst: Packed[Scalar], rsync: bool = False, rneg: bool = False, msg: str | None = None) → Assumption

assert_seq(name: str, p: Expr, s, xs, clk: Packed[Scalar], rst: Packed[Scalar], rsync: bool = False, rneg: bool = False, msg: str | None = None) → Assertion

assume_next(name: str, p: Expr, q: Expr, clk: Packed[Scalar], rst: Packed[Scalar], rsync: bool = False, rneg: bool = False, msg: str | None = None) → Assumption

assert_next(name: str, p: Expr, q: Expr, clk: Packed[Scalar], rst: Packed[Scalar], rsync: bool = False, rneg: bool = False, msg: str | None = None) → Assertion

class seqlogic.Logic(name: str, parent: Module, dtype: T)

property dtype: T

class seqlogic.Packed(name: str, parent: Module, dtype: T)

Leaf-level bitvector design component.

is_neg() → bool

Return True when bit is stable 0 => 0.

is_posedge() → bool

Return True when bit transitions 0 => 1.

is_negedge() → bool

Return True when bit transitions 1 => 0.

is_pos() → bool

Return True when bit is stable 1 => 1.

is_edge() → bool

Return True when bit transitions 0 => 1 or 1 => 0.

async posedge()

Suspend; resume execution at signal posedge.

async negedge()

Suspend; resume execution at signal negedge.

async edge()

Suspend; resume execution at signal edge.

class seqlogic.Unpacked(name: str, parent: Module, dtype: T)

Leaf-level array of vec/enum/struct/union design components.