Design Elements

Design Elements#

exception seqlogic.DesignError#: Design Error.

class seqlogic.Module#

Hierarchical, branch-level design component.

A module contains: * Submodules * Ports * Local variables * Local processes

build()#

elab() → Coroutine#: Add design processes to the simulator.

property scope: str#: Return the branch’s full name using dot separator syntax.

dump_waves(waves: defaultdict, pattern: str)#

dump_vcd(vcdw: VCDWriter, pattern: str)#

input(name: str, dtype: type[Bits]) → Packed#

output(name: str, dtype: type[Bits]) → Packed#

connect(**ports)#

logic(name: str, dtype: type[Bits], shape: tuple[int, ...] | None = None) → Packed | Unpacked#

submod(name: str, mod: type[Module]) → Module#

drv(coro: Coroutine)#

mon(coro: Coroutine)#

combi(ys: Value | list[Value] | tuple[Value, ...], f: Callable, *xs: Packed | Unpacked)#: Combinational logic.

expr(ys: Value | list[Value] | tuple[Value, ...], ex: Expr)#: Expression logic.

assign(y: Value, x: Packed | str)#: Assign input to output.

dff(q: Packed, d: Packed, clk: Packed)#

D Flip Flop.

Parameters:

q – output
d – input
clk – clock w/ positive edge trigger

dff_r(q: Packed, d: Packed, clk: Packed, rst: Packed, rval: Bits | str, rsync: bool = False, rneg: bool = False)#

D Flip Flop with reset.

Parameters:

q – output
d – output
clk – clock w/ positive edge trigger
rst – reset
rval – reset value
rsync – reset is edge triggered
rneg – reset is active negative

dff_en(q: Packed, d: Packed, en: Packed, clk: Packed)#

D Flip Flop with enable.

Parameters:

q – output
d – input
en – enable
clk – clock w/ positive edge trigger

dff_en_r(q: Packed, d: Packed, en: Packed, clk: Packed, rst: Packed, rval: Bits | str, rsync: bool = False, rneg: bool = False)#

D Flip Flop with enable, and reset.

Parameters:

q – output
d – input
en – enable
clk – clock w/ positive edge trigger
rst – reset
rval – reset value
rsync – reset is edge triggered
rneg – reset is active negative

mem_wr_en(mem: Unpacked, addr: Packed, data: Packed, en: Packed, clk: Packed)#: Memory with write enable.

mem_wr_be(mem: Unpacked, addr: Packed, data: Packed, en: Packed, be: Packed, clk: Packed)#: Memory with write byte enable.

class seqlogic.Packed(name: str, parent: Module, dtype: type[Bits])#

Leaf-level bitvector design component.

is_neg() → bool#: Return True when bit is stable 0 => 0.

is_posedge() → bool#: Return True when bit transitions 0 => 1.

is_negedge() → bool#: Return True when bit transitions 1 => 0.

is_pos() → bool#: Return True when bit is stable 1 => 1.

is_edge() → bool#: Return True when bit transitions 0 => 1 or 1 => 0.

async posedge()#: Suspend; resume execution at signal posedge.

async negedge()#: Suspend; resume execution at signal negedge.

async edge()#: Suspend; resume execution at signal edge.

class seqlogic.Unpacked(name: str, parent: Module, dtype: type[Bits])#: Leaf-level array of vec/enum/struct/union design components.